1. Field of the Invention
This invention relates to personal computer systems and, more particularly, to methods and apparatus for blending write back data from a central processing unit cache with increments of data being written to memory by a bus master in order to maintain data coherency.
2. History of the Prior Art
In order to increase the speed of operation of personal computer systems, the operational speed of central processing units has constantly been increased.
Increasing the processor clock speed is one manner by which the speed of processors is increased. State of the art processors typically run at a faster clock speed than do other components of the computer.
When the clock speed of a central processing unit is increased, the processor conducts its operations more rapidly than do other parts of a personal computer system. For example, a fast central processing unit writes to main memory much more rapidly than main memory can store the data written because memory cannot be accessed constantly at the rate of processor writes. Because of this, many prior art systems utilize write buffers on the memory bus between the central processing unit and main memory. Such a write buffer stores data at the rate at which a processor is writing to main memory while the data is not transferred to main memory until main memory is ready to accept the data. Write buffers are particularly advantageous when used with processors and other circuitry which have been designed to transfer data in bursts. Burst transfers are fast because a processor transfers a number of increments of data to be written on a memory bus or a local bus during a single bus access using only a single set of control signals. Transferring a plurality of increments of data to a write buffer allows the processor to pursue other operations using data and instructions in its caches without having to wait for the slower memory operations to complete. In this manner, the processor may be kept running at higher speeds.
Similar write buffers are now utilized in a number of computer systems for buffering data being transferred to main memory from a bus master positioned on a local bus.
Another manner in which the speed at which processors, and thus computer systems, function is increased is by the use of processor caches. A processor cache stores data and commands which have been recently used by the processor so that this information is more rapidly available to the processor than it is in main memory. In a typical system, when the processor accesses a memory address, the addressed information read from memory is sent both to the processor and to the processor cache; the information sent to the cache often includes additional information surrounding the addressed information sufficient to fill an entire cache line. The information is stored in the cache with its memory address where it is available for later use. A processor cache may be accessed in a fraction of the time required for memory access. Since software processes tend to use the same data and commands repeatedly, the information is much more likely to be accessed in the cache than in memory. The use of processor caches greatly speeds the operation of the processor.
Computer systems utilizing processors such as the i486 and Pentium manufactured by Intel Corporation of Santa Clara, Calif., utilize a relatively small high speed primary cache (called an L1 cache) which is a part of the circuitry of the processor chip and provide control circuitry for joining a larger off-chip secondary cache (called an L2 cache) to assist the primary cache.
One problem systems using processor caches have is in maintaining the coherency of data so that any data used is up to date whether it is accessed from in a cache or in main memory. In systems using processor caches, when a processor writes data to a memory address, that data is immediately sent to the primary processor cache. With processor caches which function on what is termed a "write through" basis, the data sent to the cache is also immediately written back to memory. In this manner, the same data exists in both the cache and main memory; and coherency problems do not arise. However, the need for each write to be transferred immediately to memory places a substantial load on the memory bus (as well as on other parts of the system) and may slow the operation of the system.
When a processor writes data to memory in a system using a cache which functions on what is termed a "write back" basis to maintain coherency of the data in the cache and memory, the data written immediately by the processor to the primary processor cache is written back to memory only when the data is actually needed. For example, a cache may need to write data back to memory only when the cache is flushed, when a valid cache line is deallocated to provide space for a line of new data in the cache, or when the only valid copy of data is in the processor cache and another processor wants to use, or partially overwrite, that data. In each of these cases, the only valid copy of the data may be in the cache so that a write to memory is required to assure that the data in main memory is not stale. Although most computers systems do not include multiple processors, a bus master such as a direct memory access controller (DMA), a SCSI controller, or the like often needs to read data from or write data to main memory. Consequently, computer systems having write back caches also require that data in processor caches be written back to memory before that data may be accessed by these bus master devices. The need to write data back to memory from a processor cache is obvious where a bus master must read from memory since the data it will read may be stale unless up-to-date data in the processor cache in written back to memory before the read operation.
However, when a bus master must write to memory, the processor cache must also write back modified lines to ensure that the latest data is not lost. Since it is possible the bus master to overwrite only a part of the data in a modified cache line while the cache only writes back data in cache line increments, modified data in the cache must be detected and written back to memory before the bus master write to ensure data coherency. A write of cache data which is more up-to-date than main memory data before a bus master write causes an entire cache line of modified data to replace data in memory at those memory locations corresponding to the cache line; and a write of less than a cache line from a bus master to the memory address merely updates the modified data in memory. If the cache write back were not to be performed at this time, the data from the bus master (which is considered to be the most recent) would be written over by a modified cache line and lost.
The need for write backs from the cache during bus master write operations is more obvious when error correction code (ECC) is stored with data in memory. Error correction code is generated as a part of an error correction process and is used to detect storage errors in memory arrays and correct some of those errors. An error correction process uses a math function to compute during storage an error correction code (referred to herein as a check value or ECC value) which is unique to the data stored. A check value is stored in memory in association with the data. When the data is read back, a determination is made whether the data read would produce the check value stored with the data. If the data would not produce the check value stored, some change has occurred in the data or the check value since they were stored. If the value has changed, then the data and the check value read from memory are sometimes used to accomplish the correction of the data depending on the type of error.
An ECC value is computed for an entire bus width increment of data. An ECC value for a sixty-four bit bus width increment of data stored in main memory may be eight bits. Such a value allows detection of all one and two bit errors, the detection of errors in four consecutive bits in certain types of memory, and the correction of all single bit errors. Since an ECC value is computed each time data is written to memory, a write to memory is done in bus width increments. To accomplish a write to memory of data less than the width of the memory bus (e.g., one byte or one word of a double word wide bus), a memory controller typically must read the data at the address in memory, modify the data read from memory with the new data being written, and write the modified data back to memory in a bus width increment. This is a time consuming process.
A bus master on the local bus may write to memory in less than bus length increments. If it does so when using ECC values to protect data in memory, the process is slow compared to writing bus width increments of data. More importantly, if a bus master writes a data increment less than a bus width to memory, then the data in the memory space is read back by the memory controller to complete the write. If the data in memory is stale because the only valid copy is in the processor cache, then the write to memory by the bus master will include stale data. A later write back from the processor cache may or may not update the data correctly. Consequently, the data in memory must be updated by writing back the cache data whenever a controller attempts to access a particular address for which the only valid copy is stored in the processor cache.
Because the ECC value is checked against the data to make sure that what is being read is what was stored, each time data is written to memory in increments less than the memory bus width, the controller must read, modify, and write the modified data back. Moreover, for each read step, the controller must also compare the data read and the check value to see if errors have occurred and then must compute a separate check value for each set of modified data written back to memory. For word increments written on a quad word memory bus, this requires four comparisons and four check value computations for each quad word individually written to memory.
In prior art computer systems, the process of writing back the data from a processor cache in order to update data for a write from a bus master controller and then writing the data furnished over the bus has been conducted in two separate stages. In the first stage, the data is written from the cache into the processor-to-memory write buffer and then to memory. In the second stage, the bus data is written into a bus-to-memory write buffer and then to memory. Two writes to the same location are required which slows the operation of the computer system. If either write requires a read/modify/write operation, the time for accomplishing these steps is even greater.
It is desirable to increase the speed of writing to memory from a bus master in a personal computer system using write buffers and write back caches.